This invention relates to a time division switching circuit with time slot interchange which changes the bit array of time division multiplex data from an incoming line to the other bit array, and which transmits the data thus changed to an outgoing line.
A known time division switching circuit comprises, among other things, a data buffer memory capable of random access, a time slot counter and an address control memory capable of random access or cyclic access. One-frame data consisting of a predetermined number of time slots are supplied from an incoming line and written into the data buffer memory in a specific order, using the outputs of the time slot counter as write-in addresses. The data are read out from the data buffer memory in a random order, using the outputs of the address control memory as read-out addresses, and then are transmitted to an outgoing line. This is how the time division switching operation is achieved in the known time division switching circuit. Such a time division switching circuit is disclosed in, for example, U.S. Pat. No. 3,956,593.
The data buffer memory of the known circuit is usually a random access memory (RAM). Thus, every time a new time division switching equipment is designed, it is necessary to select memory elements which operate at a proper required speed for the switching ability of the equipment, and to design a special peripheral circuit which operates at a proper timing for the selected memory elements. The known time division switching circuit is designed for a special purpose and cannot therefore be used for various purposes. If the time division switching circuit is constituted by a single LSI, which seems possible owing to the rapid progress of IC technology, it cannot be manufactured in large quantities because it fails to serve various purposes. For this economical reason, it is difficult to manufacture the circuit of this type in the form of an LSI.
Moreover, the address control memory must be provided with as many signal lines as can designate a number of time slots included in one frame, said signal lines being used for writing data into the address control memory from a switch controller. Further there must be provided signal lines for supplying various clock signals to operate the data buffer memory and the address control memory, such as chip select signals and write-enable signals or signals for latching memory outputs at various resisters. Thus, if the time division switching circuit is made of a single LSI, pins must be used in greater numbers. This will also bring up the cost of the circuit.
It is an object of this invention to provide a time division switching circuit with time slot interchange which can easily be realized in an LSI, and which can serve various purposes.